This invention relates to a transistor, and more particularly an insulated gate type transistor.
As active elements, various types of transistors have been developed. According to the current characteristics, they are classified into a transistor having a saturation type current characteristic such as a junction type bipolar transistor, a field effect transistor or the like which has the same characteristic as a pentode, and a nonsaturation type current transistor such as a static induction transistor (SIT). Various constructions have been proposed for the former type to meet various fields of applications. However, as this type has a saturating current characteristic it is not suitable for a transistor required to handle a large current. For this reason, attention has been directed to transistors as a SIT having a nonsaturating current characteristic.
As disclosed in a paper of I.E.E.E. Transactions of Electronic Devices, Vol. Ed-22, No. 4, April, 1975, pages 185-197, for example, the SIT has a fundamental construction consisting of a source region having an N.sup.+ diffused layer formed on the surface on an N type substrate, a gate region consisting of a P.sup.+ diffused layer adjacent to the source region and having a larger depth than the N.sup.+ diffused layer, and a drain region made up of an N.sup.+ diffused layer formed on the rear surface of the substrate, and wherein the thickness of a depletion layer is controlled in accordance with the magnitude of a gate voltage applied upon the gate region so as to ON/OFF-control the current path between the source region and the drain region.
Since the SIT is a unipolar element utilizing only the majority carriers as the carrier, the limit of its current density is about 10.sup.3 A/cm.sup.2. Therefore, it has a fatal defect, in that, it is impossible to have a current density higher than this upper limit. In order to manifest sufficiently high performance, it is desirable to construct an SIT having a vertical construction. Such vertical construction, however, makes it difficult to fabricate the SIT as an integrated circuit. For example, in order to fabricate the SIT into an integrated circuit, it is generally necessary to provide the drain terminal to the side of the source terminal. To this end, it is necessary to provide a burried layer having a high impurity concentration region which interconnects the burried layer to the drain electrode just like a vertical type bipolar transistor. This not only increases the number of manufacturing steps but also complicates the same and increases the serial resistance of the element. Moreover, when the SIT has a vertical construction it can be used to fabricate only two dimentional LSIs which are expected to be used frequently in the future.
In order to provide a nonsaturating characteristic to a SIT utilizing an N type silicon substrate, for example, the voltage V.sub.GS impressed between the gate electrode and the source region, and the voltage V.sub.DS impressed upon the drain region are restricted to a range expressed by a relation V.sub.GS &lt;V.sub.DS &lt;0. It is, therefore, impossible for the SIT to fabricate a circuit operating at any operating condition as well as a logic circuit similar to a conventional MOS FET.